1. Field of the Invention
The present invention generally relates to a method for testing a semiconductor integrated circuit and, more particularly, to a method for selecting operation cycles of a semiconductor integrated circuit so as to perform an IDDQ measurement in the selected operation cycles.
2. Description of the Related Art
As CMOS integrated circuits are increasingly highly integrated and are formed into fine structures, a frequency of occurrence of new fault modes which are difficult to find by a conventional functional test has been increasing. The new fault modes include an open fault and a short fault due to a fine structure of wiring between elements in a semiconductor integrated circuit. Thus, if only the functional test is performed for an inspection, a semiconductor integrated circuit which has one of the above-mentioned new faults may be delivered as a product which has passed the inspection and, thereby, the semiconductor integrated circuit having a fault may be assembled into a final product.
An IDDQ test is suggested to detect the above-mentioned new faults. In the IDDQ test, a measurement of quiescent power supply current (IDDQ) is performed so as to detect existence of a fault. Specifically, in the IDDQ test, a fine power-supply current flowing in a CMOS integrated circuit which is in a steady state (standby state) is measured so as to determine existence of a fault by a level of the power-supply current. In a normal CMOS integrated circuit, only a very small power-supply current flows. That is, if a large current flows in a CMOS integrated circuit in a standby state, this indicates that the CMOS integrated circuit includes a defect or fault therein. Although a state of an integrated circuit continuously changes during a normal operation, the IDDQ test can be performed during an operation cycle which is in a standby state.
A technique to detect the standby cycle by using logical simulation is known. For example, Japanese Laid-Open Patent Application No. 4-44172 suggests determining an operation cycle to be one which is in the standby state when the following four conditions are satisfied.
1) Output signals of a plurality of gates are not in conflict with each other (not a bus conflict state).
2) All of the gates connected to a bus are not in a high-impedance "Z" state.
3) A logical value at a node with a pull-up is in a high level "H".
4) A logical value at a node with a pull-down is in a low level "L".
If only a quality of test is considered, that is, if only a capability of detection of a fault is of concern, it is better to perform a test during various states of an operation. Accordingly, it is most appropriate to perform the test for all cycles in which the standby state is achieved. However, in practice, a number of the standby cycles used for the test should be as small as possible since a time for performing the test directly influences a manufacturing cost. That is, it is desired to reduce a time spent on the test as much as possible while maintaining a quality of a result of the test above an allowable level.
The IDDQ test includes measurement of a current as mentioned above. Generally, measurement of a current takes a longer time than that of measurement of a voltage. In order to reduce a time spent on the test, the number of measurements should be reduced. Accordingly, is it desired to select the number of standby cycles which is sufficient for maintaining a certain level of the quality of the test result. The following two papers suggest methods for selecting the standby cycles.
1) Kazuo Wakui, Toshinobu Ono and Masaaki Yoshida, "A pattern selection algorithm for IDDQ test", proceedings of 1995 Electronic Information Communication Electronics Society Conference, vol.2, p.185, C-463, September 1995.
First, an operator designates a number "n" of cycles in which the IDDQ test is performed. Then, a logical simulation is performed by inputting test patterns for a functional test so as to select and extract first n standby cycles. Then, a fault coverage is calculated for the n IDDQ tests. Thereafter, subsequent standby cycles are investigated one by one so as to check if the fault coverage is improved when each of the subsequent standby cycles is replaced with one of the first n standby cycles. If there is a standby cycle which improves the fault coverage, the standby cycle is replaced with the one of the first n standby cycles. This operation is performed with respect to all of the subsequent standby cycles.
2) Weiwei Mao, Ravi K. Gulati, Deepak K. Goel and Michael D. Ciletti, "QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage Faults", proceedings of the 1990 ICCAD conference held by IEEE, pp.280-283.
In the method disclosed in this document, a logical simulation is performed while referring to a fault table which is previously prepared by an operator. The fault table indicates which state of input corresponds to which type of fault with respect to each of the gates in a circuit. If the operator does not designate a number "n" of test cycles in which the IDDQ test is performed during execution of the logical simulation, a cycle from which at least one new fault can be detected is added to the test cycles. On the other hand, if the operator designates the number "n" of the test cycles, a cycle from which a number of new faults to be detected is greater than an expected number of faults per one cycle is added to the test cycles.
In the method suggested by Wakui et al., there is a problem in that an operator must designate the number "n" of the test cycles. That is, the number of cycles sufficient for obtaining a desired accuracy of detection cannot be decided previously. Accordingly, the operator is forced to designate an uncertain number of cycles. Thus, the number of cycles designated by the operator may be insufficient for obtaining a desired result, or may be in excess. Whichever happens, an appropriate number of cycles cannot be obtained in most cases.
Additionally, in the method suggested by Wakui et al., there is another problem in that a possibility for replacement of one of the first n standby cycles must be checked with all of the standby cycles subsequent to the first n standby cycles, and this operation takes a long time. In an extreme case, the first n standby cycles may remain at the end of the operation for checking a possibility of replacement. However, even in such a case, all standby cycles must be checked in this method. Thus, a time is wasted for the checking operation. Especially, if the number of test patterns for a functional test is extremely large, such a wasted time may be a serious problem.
In the method suggested by Mao et al., there is a problem in that the fault table must be prepared previously although the fault table once prepared can be commonly used for other circuits. This method also has the same problem as the method suggested by Wakui et al. when the number "n" of cycles for performing the IDDQ test is designated by an operator. Additionally, there may be a problem in that a result desired by the operator cannot be obtained when the operator does not designate the number "n" of cycles for performing the IDDQ test.
Consideration will now be given of a case in which all faults can be detected by the last two cycles of a series of operation cycles in the test patterns for a functional test. In this case, since the operation cycles are sequentially checked with respect to passage of time, it is possible that cycles preceding the last two cycles are selected. As a result, there is a problem in that an excessive number of standby cycles are selected for the IDDQ test.
As mentioned above, a manufactured semiconductor integrated circuit device must be subjected to a function test so as to check functional operations thereof. A part of a fault found in such a function test may be detected in the IDDQ test which is performed after the function test is completed so as to supplement the function test.
However, the conventional IDDQ test does not consider the above-mentioned matter. That is, the conventional IDDQ test is performed while selecting and extracting test cycles or test patterns with all faults as targets to be detected. Accordingly, the conventional IDDQ test has the following problems.
1) A time for testing a semiconductor integrated circuit device is unnecessarily increased, which directly causes an increase in a manufacturing cost of the semiconductor integrated circuit device.
2) A time spent by an IDDQ test apparatus for checking a single semiconductor integrated circuit device is unnecessarily increased, which increases a manufacturing cost of the semiconductor integrated circuit device.